Sami Yehia

Many times the difference between failure and success is doing a thing nearly right and doing it exactly right.

Edward C. Simmons

Visits since June 08

  • Last Update : 1st of january 2011
  • RESEARCH INTERESTS

    • Computer achitectures, compilers and embedded systems, more specifically
    • Architecture Specialization and Instruction set customization, transparent customization.
    • Multicore architectures and heterogeneous parallel systems.
    • Parallel programming models.
    • Architectures for safety-critical systems
    • SIMD architectures.

    EDUCATION

    • Ph.D. in Computer Science, Computer Architecture, Paris-Sud (Paris XI) University, Orsay, France. September 2004
      Ph.D. Thesis Title: "Alternative Approaches to Improve Performance without ILP"
      Defense Jury: André SEZNEC (IRISA/INRIA), Sanjay PATEL (University of Illinois at Urbana Champaign),  Marc DURANTON (Philips Research) and Olivier TEMAM ( Paris-Sud XI University)
      September 2004, Advisor: Professor Olivier Temam.
    • Master Degree in Parallel Architectures, Paris-Sud University, Orsay, France. July 2000
      "Méthodologie d'évaluation des architectures des processeurs," Advisor: Professor Olivier Temam.
      Major on writing exams.
    • Master Degree In Computer Engineering, Arab Academy for Science and Technology, Alexandria, Egypt. September 1999
      Master Thesis title: "Architectural Level Synthesis in A Reconfigurable Environment,"  Advisors: Dr. Yasser Y. Hanafy  and Professor Youssry Y. El Gamal.
      GPA: 4.0/4.0.
    • BSc in Computer Science and Automatic Control. Faculty of Engineering, Alexandria University.  June 1995
      Excellent with degree of honor ranked 5th

    PUBLICATIONS

    Conferences and Workshops

    • Sylvain Girbal, Olivier Temam, Sami Yehia, Hugues Berry, and Zheng LI, "A memory interface for multi-purpose multi-stream accelerators," ACM International conference on Compilers, architectures and synthesis for embedded systems (CASES), October 2010.
    • Dominik Auras, Sylvain Girbal, Hugues Berry, Olivier Temam and Sami Yehia, "CMA: Chip multi-accelerator," IEEE 8th Symposium on Application Specific Processors (SASP), June 2010.
    • Sami Yehia, Sylvain Girbal, Hugues Berry, and Olivier Temam, "Reconciling Specialization and Flexibility Through Compound Circuits," International Symposium on High-Performance Computer Architecture (HPCA), February 2009.
    • Nathan Clark, Amir Hormati, Scott Mahlke, Sami Yehia, and Krisztian Flautner, "Liquid SIMD: Abstracting SIMD Hardware Using Lightweight Dynamic Mapping," International Symposium on High-Performance Computer Architecture (HPCA), February 2007. Highest ranked paper of 174 submissions
    • Nathan Clark, Amir Hormati, Scott Mahlke, and Sami Yehia, "Scalable Subgraph Mapping for Acyclic Computation Accelerators," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2006.
    • Sami Yehia, Nathan Clark, Scott Mahlke, and Krisztian Flautner, "Exploring the Design Space of LUT-based Transparent Accelerators, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005. Best Paper Award.
    • Jean-Francois Collard, Norm Jouppi and Sami Yehia, "System-Wide Performance Monitors and their Application to the Optimization of Coherent Memory Accesses," ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'05), June 2005.
    • Sami Yehia, Jean-François Collard and Olivier Temam, "Load Squared: Adding Logic Close to Memory to Reduce the Latency of Indirect Loads with High Miss Ratios, MEDEA Workshop, held in conjunction with the International Conference of Parallel Architectures and Compilation Techniques (PACT),  October 2005.
    • Sami Yehia and Olivier Temam, "From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation," 31th Annual International Symposium on Computer Architecture (ISCA), June 2004.
    • Sami Yehia and Olivier Temam, "From Sequences of Dependent Instructions to Functions: A Complexity Effective Approach for Improving Performance without ILP or Speculation," 4th Workshop on Complexity-effective Design (WCED) held in conjunction with the 30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
    • Sami Yehia and Yasser Y. Hanafy, "Optimal Module Selection and Scheduling of Dynamically Reconfigurable Processors, 9th International Conference on Computer Theory and applications (ICCTA' 99), 1999, Alexandria Egypt.

    Journal papers

    • Arnaud Grasset, Philippe Millet, Philippe Bonnot, Sami Yehia, Wolfram Putzke-Roeming, Fabio Campi, Alberto Rosti, Michael Huebner, Nikolaos S. Voros and Davide Rossi, "The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform", International Journal of Parallel Programming. (IJPP), Volume 38, 2010.
    • Sami Yehia, Jean-François Collard and Olivier Temam, "Load Squared: Adding Logic Close to Memory to Reduce the Latency of Indirect Loads in Embedded and General Systems," Journal of Embedded Computing (JEC), Volume 2, Number 1, January 2006, IOS Press.

    Other posters and talks

    • Chatti, Majed; Yehia, Sami; Timsit, Claude; Zertal, Soraya; , "A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications," Poster paper, International Conference on High Performance Computing and Simulation (HPCS), June 2010
    • Marios Kleanthous, Sami Yehia, Yiannakis Sazeides, Emre Ozer, "A Replacement Policy Based on Dynamic Profiling and Hashed Information," Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), July 2007.
    • Philippe Bonnot, Sami Yehia, Arnaud Grasset, Eric Lenormand, Gilbert Edelin, "Mapping high performance and mission-critical applications to Embedded Architectures," 4th HiPEAC Industrial Workshop on Compilers and Architectures, November 2007
    • HiPEAC Roadmap

    • Marc Duranton, Sami Yehia, Bjorn De Sutter, Koen De Bosschere, Albert Cohen, Babak Falsafi, Georgi Gaydadjiev, Manolis Katevenis, Jonas Maebe, Harm Munk, Nacho Navarro, Alex Ramirez, Olivier Temam, Mateo Valero, "The HiPEAC Vision ", 2012-2020 Roadmap of the FP7 Network of Excellence on High Performance and Embedded Architecture and Compilation, January 2010

    WORK EXPERIENCE

    • Currently Staff Research engineer at Thales Research & Technology (since April 2007) - Embedded Syslem Lab - Research engineer in the field of processor architecture.
    • Staff Research Engineer at ARM ltd, Cambridge, UK. From October 2004 to April 2007. Research engineer in processor architecture, R & D division
    • Summer Internship at HP Palo Alto, CA - System Architecture Department. From July 2004 to October 2004.
    • Teaching Assistant (ATER) - Computer Science, Paris-Sud University, Orsay, France. From October 2003 to July 2004.
      Courses: Computer Architecture, Unix, Java Programming (Project).
    • Teaching Assistant (Moniteur) - Computer Science, Paris-Sud University, Orsay, France. From October 2000 to August 2003.
      Courses: Principles of languages interpretation, Functional programming, Digital logic, Computer Architecture.
    • Teaching Assistant - Arab Academy for science and technology, College of engineering, Department of computer engineering. From October 1995 to June 1999.
      Courses: Programming (Basic, Pascal, C), Object Oriented design, Numerical analysis, Computer Architecture, Databases, Data structures, Operating systems, Discrete mathematics, Digital design and software engineering.
    • Part time Instructor - American University of Cairo, Branch of Alexandria From 1996 to 1999
      Courses: Ms-Word, MS-Access, MS-DOS, Introduction to Computers, Windows95, PASCAL, C Programming Language, Operating Systems, Numerical Analysis.
    • Design and development of an Accounting database under Visual Basic 6.0, MS-SQL server 7.0, for Salamarine Egypt, 1999.
    • Participate in the design and development of a shipping and container database under MS-Access, for Marina Shipping Agency, 1998.
    • Participate in the installation and starting of a Cyber- Café, Access Cyber Café in Alexandria, 1996.
    • BSc Project: Digital control of a heat rig, under Borland C++ , 1995.
    • Summer Internship Training at WEPCO (Western Desert Operating Petroleum Co.), 1993.
    • Summer Internship at ANACAD Computer Systems, Grenoble, France, 1992.

    Patents

    • Sami Yehia, Krisztian Flautner, "Instruction subgraph identification for a configurable accelerator," United State patent US2007220235, September 2007
    • Sami Yehia, Krisztian Flautner, "Data Processing Apparatus and Method for Accelerating Execution Subgraphs," WIPO patent WO2006136764, United States Patent Application 20080263332, October 2008
    • Sami Yehia, Krisztian Flautner, Nathan Clark, Amir Hormati, Scott Mahlke, "Translation of SIMD instructions in a data processing system," United State patent US2008141012, June 2008
    • Sami Yehia, Marios Kleanthous, "Entry replacement within a data store," United States Patent 20080183986, July 2008
    • Yehia, S., Temam, O. and Berry, H. (2010) "Procédé pour la conception d'accélérateurs", Patent # FR2937762, Institut National de la Propriété Industrielle, France, April 2010
    • Sami Yehia, "Système Multiprocesseur", Patent # FR2938943, Institut National de la Propriété Industrielle, France, May 2010
    • Sami Yehia, "Multiprocessor system", United State Patent 20100153685, June 2010

    OTHER RESEARCH ACTIVITIES

    • Member of the HiPEAC Network and member of its Industrial Advisory Board
    • Vice chair of the editorial board of the HiPEAC Roadmap
    • Technical Program Committee Member
      • SASP 2011 (IEEE Symposium on Application Specific Processors), Program Chair
      • IFMT'10: 2nd International Forum on Next Generation Multicore/Manycore Technologies, Program chair.
      • PPES 2011, Bringing Theory to Practice: Predictability and Performance in Embedded Systems Workshop co-located with DATE 2011
      • ARCS 2010 (Architectures of Systems and Compilers). Program chair.
      • SAC 2011, 25th ACM Symposium on Applied Computing, Embedded Systems Track
      • DATE 2011 , D9 Architectural and Microarchitectural Design Track, Program chair
      • ICCD 2010 (IEEE International Conference on Computer Design)
      • SEUS 2010 (The 8th IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems)
      • SAMOS 2009 (International Symposium on Systems, Architectures, MOdeling and Simulation)
      • SAC 2010, 25th ACM Symposium on Applied Computing, Embedded Systems Track
      • ARCS 2010 (Architectures of Systems and Compilers). Program chair.
      • DATE 2009 (Design , Automation and Test in Europe)
      • SAMOS 2009 (International Symposium on Systems, Architectures, MOdeling and Simulation)
      • ICCD 2009 (IEEE International Conference on Computer Design)
      • CF2009 (Computing Frontiers)
      • SASP 2009 (IEEE Symposium on Application Specific Processors)
      • CASES 2009 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).
      • ARCS 2009 (Architectures of Systems and Compilers).
      • ICCD 2008 (IEEE International Conference on Computer Design - Processor Architecture Track)
      • SASP 2008 (IEEE Symposium on Application Specific Processors)
      • SAMOS 2008 (International Symposium on Systems, Architectures, MOdeling and Simulation)
      • IFMT 2008 (First International Forum on Next-Generation Multicore/Manycore Technologies)
      • ICCD 2007 (IEEE International Conference on Computer Design)
      • WASP 2008 (IEEE Workshop on Application Specific Processors)
      • CASES 2007 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).
      • IISWC 2007 (IEEE International Symposium on Workload Characterization - benchmark committee)
      • CASES 2006 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).
      • ARCS 2006 (Architectures of Systems and Compilers).
    • Reviewer for International Conferences and workshops: ISPASS 2004, ASPLOS 2004, LCTES 2005, PACT 2005, CODES+ISSS 2005, CASES 2005, HIPEAC 2005, MOBS 2006, WASP 2006, DATE 2006, ISCA 2006, MICRO 2006, HPCA 2009, HiPEAC 2009, ISPASS 2009, ISCA 2010
    • Reviewer for International Journals: JSA (Journal of Systems and Architectures), IEEE TCAD Transactions, ACM Transactions on Architecture and Code Optimization (TACO), ACM Transactions on Embedded Computing Systems(TECS), IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
    • Special Session Chair, IEEE 8th Symposium on Application Specific Processors (SASP), June 2010.

    OTHER TRAINING AND COURSES

    • Business Development and Growth - Holden Intl - April 2007
    • ARM RealView Soc Designer (MaxSimâ„¢) - 2006
    • Time Management - Cambrdge, UK - December 2006
    • Course at MICROSOFT Egypt: Microsoft SQL SERVER - System Administration (6 days), 1999.

    COMPUTER AND LANGUAGE SKILLS

    • Languages: C, C++, PROLOG, SQL, HTML, VBA, Pascal, Basic, Java, CAML, Perl, Php scripting languages, Verilog Hardware Language..
    • Software and tools: Xilinx Foundation Series, Visual Studio, Word, Excel , Access, Power Point, MS SQL Server, FrontPage, PVM, ARM RealView Soc Designer (MaxSim™), ARM RealView Core Generator (MaxCore™), Synopsys synthesis tools.

    LANGUAGES

    • French: Native language
    • English: Fluent
    • Arabic: Fluent

    OTHERS

    • GRE:Graduate Record Examination, ETS (1996).
      • Verbal: 410 (29% below).
      • Quantitative: 760 (92% below).
      • Analytical: 710 (88% below)
      • Subject (Computer Science) : 760 (82% below)
    • TOEFEL: Test of English As A Foreign Language, ETS
      Score : 637 (old score scale in 1996 = 270 on new scale)
    Made on a mac